| Code | Mnemonic | Description |
|---|---|---|
| 0F 03 / r | LSL r16, r/m16 | Load segment limit (selector r/m16) into r16 |
| 0F 03 / r | LSL r32, r/m32 | Load segment limit (selector r/m32) into r32 |
Loads the unscrambled segment limit from the segment descriptor specified with the second operand (source operand) into the first operand (destination operand) and sets the ZF flag in the EFLAGS register. The source operand (which can be a register or a memory location) contains the segment selector for the segment descriptor being accessed. The destination operand is a general-purpose register.
The processor performs access checks as part of the loading process. Once loaded in the destination register, software can compare the segment limit with the offset of a pointer.
The segment limit is a 20-bit value contained in bytes 0 and 1 and in the first 4 bits of byte 6 of the segment descriptor. If the descriptor has a byte granular segment limit (the granularity flag is set to 0), the destination operand is loaded with a byte granular value (byte limit). If the descriptor has a page granular segment limit (the granularity flag is set to 1), the LSL instruction will translate the page granular limit (page limit) into a byte limit before loading it into the destination operand. The translation is performed by shifting the 20-bit "raw" limit left 12 bits and filling the low-order 12 bits with 1s.
When the operand size is 32 bits, the 32-bit byte limit is stored in the destination operand. When the operand size is 16 bits, a valid 32-bit limit is computed; however, the upper 16 bits are truncated and only the low-order 16 bits are loaded into the destination operand.
This instruction performs the following checks before it loads the segment limit into the destination register:
If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no value is loaded in the destination operand.
| Type | Name | Valid |
|---|---|---|
| 0 | Reserved | No |
| 1 | Available 16-bit TSS | Yes |
| 2 | LDT | Yes |
| 3 | Busy 16-bit TSS | Yes |
| 4 | 16-bit call gate | No |
| 5 | 16-bit/32-bit task gate | No |
| 6 | 16-bit interrupt gate | No |
| 7 | 16-bit trap gate | No |
| 8 | Reserved | No |
| 9 | Available 32-bit TSS | Yes |
| A | Reserved | No |
| B | Busy 32-bit TSS | Yes |
| C | 32-bit call gate | No |
| D | Reserved | No |
| E | 32-bit interrupt gate | No |
| F | 32-bit trap gate | No |
| Operands | Bytes | Clocks | |
|---|---|---|---|
| r16, r16 | 3 | 8 | NP |
| r32, r32 | 3 | 8 | NP |
| r16, m16 | 3 + d(0, 2) | 8 | NP |
| r32, m32 | 3 + d(0, 2) | 8 | NP |
| ID | unaffected | DF | unaffected |
|---|---|---|---|
| VIP | unaffected | IF | unaffected |
| VIF | unaffected | TF | unaffected |
| AC | unaffected | SF | unaffected |
| VM | unaffected | ZF | sets to 1 if the segment limit is loaded successfully; otherwise, it is cleared to 0 |
| RF | unaffected | AF | unaffected |
| NT | unaffected | PF | unaffected |
| IOPL | unaffected | CF | unaffected |
| OF | unaffected |